Axera Selected as 2024 Xuantie Preferred Partner: Advancing AI Computing and Collaborating with RISC-V to Reshape Industries

Published: March 15, 2024

“As an open instruction set architecture, RISC-V is regarded as a new engine driving the development of next-generation information technology, and its ecosystem has continued to grow and thrive in recent years.”

On March 14, 2024, the second Xuantie RISC-V Ecosystem Conference, themed "Openness · Connectivity," was held in Shenzhen. Industry experts, technology leaders, corporate decision-makers, and RISC-V community developers from around the globe gathered to witness the latest advancements of Xuantie RISC-V in technological innovation, application expansion, and ecosystem achievements. Axera, a company specializing in AI vision chip R&D and foundational computing platforms, was invited to attend.

The conference also announced the "Xuantie Preferred Partners," with Axera and seven other companies selected. This honor aims to accelerate the implementation of Xuantie ecosystem achievements, connect the RISC-V industry chain, and foster the growth of Xuantie’s commercial ecosystem. Axera’s inclusion recognizes its contributions to the Xuantie RISC-V ecosystem. At the event, Liu Jianwei, Co-founder and Vice President of Axera, delivered a keynote speech, introducing the company’s Axera Tongyuan Hybrid Precision NPU—an AI processor designed for edge and endpoint computing—and sharing insights into AI computing enhancements and industry applications based on the RISC-V ecosystem.

AI Everywhere: RISC-V Powers AI Computing
       From cloud-based large models like ChatGPT to edge computing devices and endpoint cameras, AI has become ubiquitous with rapid technological advancements. In scenarios such as autonomous driving, smart robotics, smart factories, smart cities, and intelligent retail, AI is driving productivity improvements across industries.

As a platform-level chip company focused on edge and endpoint intelligence, Axera’s mission is to "Democratize AI for a Better Life," dedicating itself to the development of high-performance, low-power AI vision processors. Liu Jianwei highlighted that Axera’s chip products have been widely adopted in AIoT and ADAS product lines, enabling robust deployment of AI at the edge and endpoints.

However, deploying AI at the edge and endpoints demands higher computing power. Here, the simplicity, flexibility, and efficiency of the RISC-V instruction set architecture stand out, positioning it as a core architecture for processors in the era of ubiquitous connectivity. As a Xuantie Preferred Partner, Axera showcased its industry applications leveraging Xuantie RISC-V. For example, in IoT, Axera combines its self-developed Axera Zhimou AI-ISP and Tongyuan Hybrid Precision NPU with Xuantie RISC-V processors to achieve rapid, low-power AI detection and wake-up, significantly reducing system power consumption and meeting the needs of battery-powered devices.

Additionally, Axera has integrated its Tongyuan Hybrid Precision NPU with Xuantie RISC-V IP to create a high-efficiency AI computing platform. This platform supports compute-intensive applications like image segmentation and text-to-image search, addressing diverse requirements for perception, computation, and data processing in edge scenarios.

Building Native AI Processors: Collaborating with Xuantie RISC-V to Reshape Industries
       Computing power is the foundation of AI. But what kind of computing infrastructure does the AI era require?

Liu Jianwei noted that as AI programs grow denser in computation, the industry needs dedicated Neural Processing Units (NPUs). "An NPU, as an AI-specific processor, should have its own instruction set rather than being treated merely as an accelerator or an extension of existing instruction sets," he explained. In AI computing, operations target high-dimensional tensors, requiring processors to focus energy on data computation while minimizing overhead from data movement and reorganization. From an inference perspective, most AI algorithms/operators have stabilized. Therefore, designing NPUs with operators—the basic computational units of AI models—as instruction sets unlocks greater flexibility in hardware microarchitecture design, improving energy efficiency.

Axera’s Tongyuan Hybrid Precision NPU, a self-developed core technology, is designed precisely around operator-based atomic instruction sets. It employs a multi-threaded heterogeneous multi-core architecture to optimize operators, network microstructures, data flow, and memory access. The NPU natively supports mixed-precision algorithms and Transformer network structures, laying a solid foundation for deploying large models at the edge and endpoints.

Moreover, the Tongyuan Hybrid Precision NPU comes with a mature, user-friendly compiler, drastically reducing AI software development and deployment costs. This allows customers to get started within an hour, accelerating the proliferation of AI computing.

In terms of performance metrics for vision-oriented AI processors, Axera’s Tongyuan Hybrid Precision NPU excels. When running SwinT, it achieves a quantization accuracy of 80.45%—surpassing industry averages—alongside high performance (416 FPS) and low power consumption (199 FPS/W).

To meet diverse AI computing needs, NPUs must also offer dynamic control flexibility. This drives Axera’s deep collaboration with Xuantie RISC-V. The company is exploring generative AI solutions by combining Xuantie RISC-V controllers with its Tongyuan Hybrid Precision NPU.

"We aim to collaborate with Xuantie RISC-V to build the optimal AI hardware platform, bringing AI to every industry and helping customers enhance efficiency and create value," Liu Jianwei concluded.